Digital signals are conventionally transmitted through various media, such as hard-wire lines and radio links. They are transmitted at a certain rate or frequency. For decoding these signals upon reception, the frequency and phase of the originally transmitted signal must be recovered. The recovered clock is applied to a sampling circuit where it determines the rate at which this circuit samples the pulses comprising the received signal.
When the digital signal is pure binary, generating a recovered signal from the received digital signal is relatively simple. A pure binary signal is comprised of nonband-limited square wave-like signals with the high portion of the square wave representing a logic one and the low-portion--a logic zero. Although the leading edge of the pulse of the recovered clock does not begin in the middle of each bit of the binary signal but may vary by as much as .+-.90.degree., the timing of the recovery clock is still adequate for instructing a decoder when to sample the bits of the incoming pure binary digital signal.
The transmission of a pure binary digital signal requires a substantial bandwidth and therefore it is usually preferable to transmit a band-limited digital signal. Moreover, for more efficient data transmission, it is desirable to transmit more than one stream of data on a single digital signal. A digital signal having more than two logic levels, i.e., more than one data stream of logic ones and logic zeros, is a multi-level digital signal. To reduce the occupied bandwidth, the multi-level digital signal is band-limited. To recover the original data streams from the band-limited multi-level digital signal, either the leading or the trailing edges of the recovered clock pulses which time the sampling circuit must ideally begin at the centre of each multi-level digital bit to ensure that none of the incoming information is lost.
A clock signal may be recovered from the transmitted multi-level signal by means for square law extraction using adjustable LC filters. Such filters are complex and costly, require initial adjustment and their responses are inclined to drift with time and temperature.
This invention seeks to provide a clock recovery circuit for deriving clock signals from band-limited multi-level digital signals in which no clock information is included, and in which the above mentioned disadvantages are mitigated.
According to the present invention there is provided a clock recovery circuit for deriving a clock signal from a band-limited multi-level digital signal, the circuit comprising means responsive to the multi-level digital for deriving a marking signal comprising groups of transition markers each marker corresponding to the crossing by the digital signal of any of a plurality of predetermined threshold levels and adjacent groups of markers being separated by an eye interval during which no transitions take place; a signal source for providing clock pulses and window pulses and means for synchronizing the window pulses with the eye intervals to provide the recovered clock signal.
The means for deriving the marking signal may include a plurality of comparators each for comparing the multi-level digital signal with any of a plurality of threshold levels and for providing an output level change indicative of the crossing of any of the plurality of threshold levels by the digital signal.
Gating means may be provided for combining outputs of the comparators into a single output.
A differentiator may be provided for differentiating logic level changes at the single output of the gating means, to provide the marking signal.
The signal source may comprise an oscillator whose output signal is fed to clock a feedback connected shaft register operative to divide the oscillator output signal to produce a train of window pulses each of predetermined width and of a repetition frequency substantially corresponding to that of the eye intervals.
The means for synchronizing the window pulses with the eye intervals may conveniently comprise means for comparing the window pulses fed from the signal source with the marking signal and for providing a synchronization indicating output signal; and synchronization adjustment means for adjusting the phase and the window pulses provided by the signal source in dependence upon the indication of the synchronization indicating output signal.
The synchronization adjustment means may conveniently comprise a flip-flop circuit having an output whose state is set in dependence upon the indication of the synchronization indicating output signal, the output of the flip-flop circuit being coupled to a control signal input of the signal source to provide adjustment of the phase of the window pulses provided by the signal source.
Advantageously smoothing means may be provided for smoothing phase jitter present in the recovered clock signal.
In an embodiment of the invention the smoothing means comprises a phase locked loop circuit including a controllable oscillator for providing a smooth clock signal; a phase comparator for comparing the phase of the clock pulses with that of the smoothed clock signal and for providing a control signal for the controllable oscillator.
Means may be provided responsive to the locking condition of the phase locked loop circuit for controlling the means for synchronizing the window pulses to reduce further any phase jitter present in the recovered clock signal.